1. Field of the Invention
The present invention relates to a differential amplifier arrangement including a differential pair having comprising two individual amplifier branches with first and second input terminals and connected at a junction point to a common branch which includes a current source, the current of the current source being regulated by a control circuit so as to linearize an input/output characteristic of the differential pair.
2. Background Information
Such a differential amplifier arrangement is already known in the art, e.g. from the book "Analogue IC design: the current-mode approach", edited by C. Tomazou et al, IEEE circuits and systems series 2, 1990, pages 197-202, and more particularly FIG. 5.12 thereof. In this known arrangement a control circuit is used to linearize the input voltage/output current characteristic of the differential pair. This linearization is obtained by keeping the gain or the transconductance (gm) of the amplifier independent of the differential input voltage across the input terminals. To this end the control circuit includes an auxiliary differential pair of NMOS transistors which are controlled by the first and the second input terminals, and in which drain currents are applied in common via a mirror circuit to the gate electrode of a third NMOS transistor included in the common branch and constituting a regulated current source. The source electrodes of the NMOS transistors of the auxiliary differential pair are connected to a common voltage terminal to which a constant DC voltage source needs to be connected.
A problem with this known arrangement is that the control circuit is a feed forward circuit which puts stringent demands on the matching of all the MOS transistors of the arrangement in order to achieve the required linearity. In more detail, the MOS transistors of the individual amplifier branches and these of the auxiliary differential pair have to match perfectly, as well as the PMOS transistors of the mirror circuit and the NMOS transistor of the mirror circuit with the third NMOS transistor. This leads to manufacturing constraints which are difficult to achieve.